
module  float_convert_altbarrel_shift_20g
	( 
	clock,
	data,
	distance,
	result) ;
	input   clock;
	input   [53:0]  data;
	input   [5:0]  distance;
	output   [53:0]  result;

	reg	[53:0]	sbit_piper1d;
	reg	sel_pipec3r1d;
	reg	sel_pipec4r1d;
	reg	sel_pipec5r1d;
	wire	[53:0]	smux_w0;
	wire	[53:0]	smux_w1;
	wire	[53:0]	smux_w2;
	wire	[53:0]	smux_w3;
	wire	[53:0]	smux_w4;

	always @ ( posedge clock) begin
		sbit_piper1d <= smux_w2[53:0];
		sel_pipec3r1d <= distance[3];
		sel_pipec4r1d <= distance[4];
		sel_pipec5r1d <= distance[5];
  end

	assign result  = sel_pipec5r1d ? {      smux_w4[21: 0], 32'b0} :      smux_w4[53:0];
  assign smux_w4 = sel_pipec4r1d ? {      smux_w3[37: 0], 16'b0} :      smux_w3[53:0];
  assign smux_w3 = sel_pipec3r1d ? { sbit_piper1d[45: 0],  8'b0} : sbit_piper1d[53:0];
  assign smux_w2 =   distance[2] ? {      smux_w1[49: 0],  4'b0} :      smux_w1[53:0];
  assign smux_w1 =   distance[1] ? {      smux_w0[51: 0],  2'b0} :      smux_w0[53:0];
  assign smux_w0 =   distance[0] ? {         data[52: 0],  1'b0} :         data[53:0];

endmodule

module float_convert (
	clock,
	dataa,
	result);

	input	  clock;
	input	[31:0]  dataa;
	output	[31:0]  result;



//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
	wire  sign_input = dataa[31];
	wire  [7:0]  exponent_input = dataa[30:23];
	wire  [22:0]  mantissa_input = dataa[22:0];
	wire  [7:0]  bias_value_w = 8'b01111111;
	wire  [7:0]  bias_value_less_1_w = 8'b01111110;
	wire  [7:0]  const_bias_value_add_width_res_w = 8'b10011110;

	wire  [7:0] wire_add_sub4_result = exponent_input - bias_value_w;
	wire  wire_cmpr2_aeb = exponent_input == bias_value_less_1_w;
	wire  wire_cmpr3_alb = exponent_input < bias_value_w;
	wire  exp_and = &exponent_input[7:0];
	wire  exp_or = |exponent_input[7:0];
	wire  wire_cmpr1_aeb = exponent_input == const_bias_value_add_width_res_w;
	wire  wire_cmpr1_agb = exponent_input  > const_bias_value_add_width_res_w;
	wire  [10:0]  man_bus1 = mantissa_input[10:0];
	wire  [11:0]  man_bus2 = mantissa_input[22:11];
	wire  [5:0]  power2_value_w = wire_add_sub4_result[5:0];
	wire  man_or1 = |man_bus1[10:0];
	wire  man_or2 = |man_bus2[11:0];

	reg	sign_input_reg1;
	reg	[22:0]	mantissa_input_reg;
	reg	below_lower_limit1_reg1;
	reg	below_lower_limit2_reg1;
	reg	exp_and_reg1;
	reg	exp_or_reg1;
	reg	equal_upper_limit_reg1;
	reg	exceed_upper_limit_reg1;
	reg	[5:0]	power2_value_reg;
	reg	man_or1_reg1;
	reg	man_or2_reg1;
	reg	int_or1_reg1;
	reg	int_or2_reg1;
always @ (posedge clock)begin
  sign_input_reg1 <= sign_input;
  mantissa_input_reg <= mantissa_input;
  below_lower_limit1_reg1 <= wire_cmpr2_aeb;
  below_lower_limit2_reg1 <= wire_cmpr3_alb;
  exp_and_reg1 <= exp_and;
  exp_or_reg1 <= exp_or;
  equal_upper_limit_reg1 <= wire_cmpr1_aeb;
  exceed_upper_limit_reg1 <= wire_cmpr1_agb;
  power2_value_reg <= power2_value_w;
  man_or1_reg1 <= man_or1;
  int_or2_reg1 <= man_or1;
  man_or2_reg1 <= man_or2;
  int_or1_reg1 <= man_or2;
end

//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

	wire  [5:0]  wire_add_sub5_result = power2_value_reg + 6'b000001;
	wire  [23:0] implied_mantissa_input = {1'b1, mantissa_input_reg};
	wire  [53:0] barrel_mantissa_input = {barrel_zero_padding_w, implied_mantissa_input};
	wire  [53:0] wire_altbarrel_shift6_result;

	float_convert_altbarrel_shift_20g   altbarrel_shift6
	( 
	.clock(clock),
	.data(barrel_mantissa_input),
	.distance(power2_value_reg),
	.result(wire_altbarrel_shift6_result));

	reg	sign_input_reg2;
	reg	below_lower_limit1_reg2;
	reg	below_lower_limit2_reg2;
	reg	exp_and_reg2;
	reg	exp_or_reg2;
	reg	equal_upper_limit_reg2;
	reg	exceed_upper_limit_reg2;
	reg	[5:0]	added_power2_reg;
	reg	int_or_reg2;
	reg	man_or_reg2;
always @ (posedge clock)begin
  sign_input_reg2 <= sign_input_reg1;
  added_power2_reg <= wire_add_sub5_result;
  below_lower_limit1_reg2 <= below_lower_limit1_reg1;
  below_lower_limit2_reg2 <= below_lower_limit2_reg1;
  exp_and_reg2 <= exp_and_reg1;
  exp_or_reg2 <= exp_or_reg1;
  equal_upper_limit_reg2 <= equal_upper_limit_reg1;
  exceed_upper_limit_reg2 <= exceed_upper_limit_reg1;
  int_or_reg2 <= (int_or1_reg1 | int_or2_reg1);
  man_or_reg2 <= (man_or1_reg1 | man_or2_reg1);
  //wire_altbarrel_shift6_result
end

//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

  wire max_shift_reg_w = added_power2_reg > 6'b011110;
	wire  [31:0]   wire_add_sub7_result_temp = lbarrel_shift_w + 31'b0000000000000000000000000000001;
	wire  wire_add_sub7_cout = wire_add_sub7_result_temp[31];
	wire  [30:0]   wire_add_sub7_result = wire_add_sub7_result_temp[30:0];
	wire  [30:0]  lbarrel_shift_w = wire_altbarrel_shift6_result[53:23];
	wire  guard_bit_w = wire_altbarrel_shift6_result[23];
	wire  round_bit_w = wire_altbarrel_shift6_result[22];
	wire  [21:0]  sticky_bus = wire_altbarrel_shift6_result[21:0];
	wire  sticky_or = |sticky_bus[21:0];
  
	wire  add_1_w = ((((~ guard_bit_w) & round_bit_w) & sticky_or) | (guard_bit_w & round_bit_w));
	wire  add_1_cout_w = ((wire_add_sub7_cout & add_1_w) & (~ sign_input_reg2));
	wire  more_than_max_shift_w = ((max_shift_reg_w & add_1_cout_w) & (~ below_lower_limit2_reg2));
	wire  upper_limit_w = exceed_upper_limit_reg2 | (sign_input_reg2 ? (equal_upper_limit_reg2 & (int_or_reg2 | add_1_w)) : (equal_upper_limit_reg2));
	wire  lowest_integer_selector = (below_lower_limit1_reg2 & man_or_reg2);
	wire  [30:0]  integer_rounded_tmp = add_1_w ? wire_add_sub7_result : lbarrel_shift_w;
	wire  [30:0]  lowest_integer_value = {barrel_zero_padding_w, 1'b1};
	wire  [30:0]  integer_rounded = lowest_integer_selector ? lowest_integer_value : integer_rounded_tmp;

	reg	below_lower_limit2_reg4;
	reg	exceed_upper_limit_reg4;
	reg	exp_and_reg4;
	reg	exp_or_reg4;
	reg	[30:0]	integer_rounded_reg;
	reg	lowest_int_sel_reg;
	reg	man_or_reg4;
	reg	max_shift_exceeder_reg;
	reg	sign_input_reg4;
always @ (*)begin
  sign_input_reg4 <= sign_input_reg2;
  below_lower_limit2_reg4 <= below_lower_limit2_reg2;
  exp_and_reg4 <= exp_and_reg2;
  exp_or_reg4 <= exp_or_reg2;
  man_or_reg4 <= man_or_reg2;
  lowest_int_sel_reg <= lowest_integer_selector;
  exceed_upper_limit_reg4 <= upper_limit_w;
  max_shift_exceeder_reg <= more_than_max_shift_w;
  integer_rounded_reg <= integer_rounded;
end
//---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------


	wire  [15:0]   wire_add_sub8_result_temp = inv_integer[14:0] + 15'b000000000000001;
	wire  [14:0]   wire_add_sub8_result = wire_add_sub8_result_temp[14:0];
	wire  wire_add_sub8_cout = wire_add_sub8_result_temp[15];

	wire  [15:0]   wire_add_sub9_result = inv_integer[30:15] + 16'b0000000000000001;
	wire  [31:0]  all_zeroes_w;
	wire  below_limit_exceeders;
	wire  [31:0]  below_limit_integer;
	wire  denormal_input_w;
	wire  exceed_limit_exceeders;
	wire  infinity_input_w;
	wire  [31:0]  infinity_value_w;
	wire  [31:0]  integer_output;
	wire  [30:0]  integer_tmp_output;
	wire  [15:0]  inv_add_1_adder2_w;
	wire  [30:0]  inv_integer;
	wire  lower_limit_selector;
	wire  nan_input_w;
	wire  [31:0]  neg_infi_w;
	wire  [31:0]  pos_infi_w;
	wire  [30:0]  signed_integer;
	wire  zero_input_w;

	wire  [29:0] barrel_zero_padding_w = {30{1'b0}};


	assign
		all_zeroes_w = {1'b0, {31{1'b0}}},
		denormal_input_w = ((~ exp_or_reg4) & man_or_reg4),
		below_limit_exceeders = (((denormal_input_w | zero_input_w) | lower_limit_selector) | nan_input_w),
		infinity_input_w = (exp_and_reg4 & (~ man_or_reg4)),
		integer_output = {sign_input_reg4, integer_tmp_output},
		integer_tmp_output = sign_input_reg4 ? signed_integer : integer_rounded_reg,
		inv_integer = (~ integer_rounded_reg),
		inv_add_1_adder2_w = wire_add_sub8_cout ? wire_add_sub9_result : inv_integer[30:15],
		lower_limit_selector = (((below_lower_limit2_reg4 & (~ zero_input_w)) & (~ denormal_input_w)) & (~ lowest_int_sel_reg)),
		nan_input_w = (exp_and_reg4 & man_or_reg4),
		neg_infi_w = {1'b1, {31{1'b0}}},
		pos_infi_w = {1'b0, {31{1'b1}}},
		signed_integer = {inv_add_1_adder2_w, wire_add_sub8_result},
		zero_input_w = ((~ exp_or_reg4) & (~ man_or_reg4)),
		exceed_limit_exceeders = (((infinity_input_w | max_shift_exceeder_reg) | exceed_upper_limit_reg4) & (~ nan_input_w)),
		below_limit_integer = below_limit_exceeders ? all_zeroes_w : integer_output,
		infinity_value_w = sign_input_reg4 ? neg_infi_w : pos_infi_w,
		result = exceed_limit_exceeders ? infinity_value_w : below_limit_integer;
endmodule
